For 7 nm and beyond nodes, with the continually increasing demand for smaller circuit structures and faster device performance, the need for increased current density has resulted in the development of nanowires, which are small structures that can be packed tightly to increase the current density of a semiconductor device. However, typically the nanowires are horizontal, and thus limited in their ability to increase current density without a penalty to the area required, or each nanowire is an isolated feature.
Therefore, it may be desirable to develop methods of fabricating nanowires that are more tightly packed and which are easily manufactured and facilitate forming new transistors.